The present specification describes a technique of correcting for differential non-linearity in an A/D converter.
Certain A/D converters, including a successive approximation A/D converter, operate based on calibrated capacitors.
A plurality of capacitors are provided. Each capacitor has a capacitance that is related to the other capacitors according to powers of 2. Hence, the capacitors produce an output charge where each represents one bit of the final digital signal. The A/D converter uses these capacitors to estimate the digital signal that it will produce.
The estimation includes changing each bit between a 1 and 0, which effectively changes the connection to each capacitor. FIG. 1 shows the connection to each capacitor C1, C2, C3, being switched between two voltages: the source voltage VDD and ground. The switching is based on whether the bit associated with that capacitor is 1 or 0. The number of switches and number of capacitors hence corresponds to the number of bits, with one capacitor being associated with one bit.
The output of the capacitor string is used by the A/D converter 100 to produce its output 102. The output 102 depends, upon other things, on the accuracy of the capacitors and their scaling.
As described above, each capacitor has a capacitance value which should be equal to a basic capacitance value Cx X 2n, where n+1 is the number of bits of resolution of the A to D converter.
Even though the capacitors are scaled relative to one another, there are often errors in the scaling. A differential non-linearity can occur based on errors in the relationship of the sizes and capacities of the capacitors. The mechanisms and causes of differential non-linearities are well known in the art.
The differential non-linearities cause certain codes in the output of the A/D converter to be missing. This effectively reduces the dynamic range of the A/D converter, causes granularity, and also may be perceived as noise. It is desirable to correct the differential non-linearity.
It has been suggested to correct a differential non-linearity by using a look-up table for each value. This, however, requires a lot of memory.
A co-pending and commonly-assigned application suggests correcting the differential non-linearity by assigning a correction value to each active bit.
The present specification teaches a different solution to solving differential non-linearity problems. This is done by adjusting an analog voltage which is placed on the capacitor. Hence, the previous-known solutions require a digital correction.
According to the preferred mode, the operation is corrected by changing the bias voltage that is applied to the capacitors. In the prior art, each of the capacitors C1, C2, . . . CN, receives the same voltage: typically the rail voltage VDD. According to this system, at least a number of the capacitors receive customized voltages which are different than the rail voltage. These voltages are customized to correct for the differential non-linearity error caused by errors in scaling of the values of the capacitors.
In a first preferred mode, the corrected voltages are produced by digital-to-analog converters which are driven by a memory storing correction values.
Another alternative which is completely analog uses a variable resistor or resistor ladder to do this.